MIPS Reference


Memory Access

Arithmetic Table of Contents Input and Output
The MIPS architecture is a Load-Store architecture. That is, only the load and store operations can be used to access memory. All other instructions operate on values in a register.

Load Instructions

MIPS provides a number of instructions to load a register. Some load a value from memory, others are used for loading addresses or immediate values.

lb rd, addr
loads a signed byte from the given memory address and stores it in register ‘rd’.
lbu rd, addr
loads an unsigned byte from memory.
lh rd, addr
loads a signed halfword from memory.
lhu rd, addr
loads an unsigned halfword from memory.
lw rd, addr
loads a word from the given memory address.
li rd, imm
loads the immediate or literal value into register rd.
la rd, addr
loads the address itself into register rd.

Store Instructions

Likewise, MIPS provides a number of store instructions.

sb rs, addr
stores the low-order byte in register rs to the given memory address.
sh rs, addr
stores the low-order halfword from register rs into memory.
sw rs, addr
stores the word from register rs into memory.
move rd, rs
copies the contents from register rs into register rd.

Address Format

The base machine uses a single addressing mode or method. Though, the virtual machine provides several additional formats. Thus, when referring to a memory address in a load or store instruction, you can use any of the following

Format Description Example
(rs) get address from register rs lw $s0, ($t0)
imm the immediate value is the address lw $s0, 50
imm(rs) immediate value plus value in register rs lw $s0, 50($t0)
label address of the label. lw $s0, x
label + imm address of the label ± immediate value. lw $s0, x+5
label + imm(rs) address of the label ± (immediate value + register rs) lw $s0, x+5($t0)


Arithmetic Table of Contents Input and Output


MIPS Processor and Assembly Language Reference

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Last modified: September 13, 2007, at 04:29 PM.